Although silicon is the dominant material technology for most electronics applications, there are significant applications for which conventional silicon technology is unsuitable. For example, optoelectronic devices (e.g., sources, modulators and detectors) are typically fabricated in compound semiconductor material systems having more favorable optoelectronic properties than silicon. However, it is difficult to monolithically integrate silicon electronics with compound semiconductor optoelectronic devices, as desired for many applications. Accordingly, various approaches for providing Si-compatible optoelectronic devices have been under development for some time. An article entitled “Silicon-based group IV heterostructures for optoelectronic applications” by Richard A. Soref and published in the Journal of Vacuum Science and Technology, pp 913-918, May/June 1996, provides a review of some of these approaches.
The use of the Si/SiGe/Ge material system is one approach under consideration for Si-compatible optoelectronics. However, the lattice mismatch of about 4% between Si and Ge is a significant complication for epitaxial growth of Ge (or Ge-rich SiGe) on silicon. A conventional approach for managing the lattice mismatch is to grow a buffer layer having a graded composition on a Si substrate, e.g., as considered in U.S. Pat. No. 6,784,466. The buffer layer composition is increasingly Ge rich as the distance from the substrate increases. In this manner, the strain introduced by the lattice mismatch can be accommodated in the buffer layer. However, this fabrication approach is disadvantageous, because the graded buffer layer may need to be relatively thick (e.g., 5-10 microns or so) which is costly, and because the resulting device chips are often mechanically fragile. It also results in a surface that is too rough for the growth of uniform, thin Ge or Ge-rich SiGe layers on thick graded buffer layers. This is commonly overcome by performing a chemical-mechanical polish (CMP) before growth of the desired epitaxial device structures. Such CMP processes further add to the cost and also expose the surface to contamination and further difficulties and limitations from regrowth on this once exposed interface. A further disadvantage of this thick graded buffer layer approach arises from the coefficient of thermal expansion (CTE) mismatch between Ge (5.90×10−6 K−1) and Si (2.57×10−6 K−1). This CTE mismatch can lead to defect formation and/or to breaking or cracking of a wafer including a thick buffer layer as temperature is varied during post-growth processing.
Management of lattice mismatch strain is particularly relevant for fabrication of quantum wells, which are often used in various optoelectronic devices. A quantum well includes a thin semiconductor well layer sandwiched between two semiconductor barrier layers. The well layer thickness is typically less than about 10 nm, and the energy bandgap of the well layer is less than the energy bandgap of the barrier layers. Further, the effective bandgap and optical properties of this well layer are dependent upon the layer thickness, hence, uniformity on a scale around 1 nm or better is extremely critical. Quantum wells in the SiGe material system are considered in U.S. Pat. No. 6,784,466 (referenced above), U.S. Pat. No. 5,886,361 and in US 2005/0141801. However, as indicated in U.S. Pat. No. 5,886,361 and US 2005/0141801, SiGe quantum wells tend to have poor electron confinement, since most of the quantum well bandgap discontinuity is in the valence band. The device of U.S. Pat. No. 5,886,361 does not require electron confinement in the quantum wells, and doping with electron donors is considered in US 2005/0141801 to improve electron confinement.
Accordingly, it would be an advance in the art to provide SiGe quantum wells having improved optical properties, especially when undoped. It would be a further advance in the art to provide such quantum wells on a Si substrate without the use of a graded buffer layer for lattice mismatch.